Information processing apparatus

ABSTRACT

By using a CR oscillating circuit and a PLL oscillating circuit selectively, these two oscillating circuits are used as a high frequency, low power consumption, short waiting time for stable oscillation, and low operating voltage oscillating circuit.

BACKGROUND OF THE INVENTION

[0001] 1. Field of the Invention

[0002] The present invention relates to an information processingapparatus, and more particularly to a technology for reducing powerconsumption in an information processing apparatus that has anoscillating circuit.

[0003] 2. Description of the Related Art

[0004] A small sized portable electronic apparatus usually works onbatteries. Therefore, in order to extend the life of the battery,one-chip microcomputers used in this kind of small sized portableelectronic apparatus are desired to be able to operate in low voltageand to be of low power consumption.

[0005] In order to realize this, one-chip microcomputers are usuallydriven at an operating voltage of around 1 voltage and at an operatingfrequency of around 32 kHz.

[0006] However, when small sized portable electronic equipment isrequired to have an information processing capability to some extent,the operating frequency of 32 kHz is not enough for processinginformation.

[0007] In order to solve this problem, a twin-clock microcomputer thathas an oscillating circuit with a low operating frequency of around 32kHz and an oscillating circuit with a high operating frequency of around4 MHz is proposed. In this twin-clock microcomputer, when high speedprocessing is required the microcomputer is driven at a high speedoperating frequency, otherwise it is driven at a low speed operatingfrequency.

[0008] Operating frequency and power consumption is in a roughlyproportional relationship, for that reason high speed processing is notdesirable from the viewpoint of power consumption.

[0009] However, recently, there is a demand for high speed informationprocessing in small sized portable electronic apparatus, and at the sametime much less power consumption is desired.

SUMMARY OF THE INVENTION

[0010] Accordingly, it is an object of the present invention to providean information processing apparatus that has capabilities of loweringpower consumption and achieving high speed information processing.

[0011] In order to achieve the above mentioned problem, the presentinvention provides an information processing apparatus comprising: afirst oscillating circuit for generating a first clock signal, the firstoscillating circuit being capable of operating until a power supplyvoltage reaches a first lowest operating voltage; a second oscillatingcircuit for generating a second clock signal, the second oscillatingcircuit being capable of operating until the power supply voltagereaches a second lowest operating voltage that is higher than the firstlowest operating voltage; a switching circuit that, based on the powersupply voltage, selects either the first clock signal or the secondclock signal to output as a clock signal; and an information processingunit, in synchronism with the clock signal, for performing informationprocessing.

[0012] According to the above configuration, the first oscillatingcircuit generates the first clock signal and outputs it to the switchingcircuit.

[0013] The second oscillating circuit generates the second clock signaland outputs it to the switching circuit.

[0014] The switching circuit, based on the power supply voltage, outputseither the first clock signal or the second clock signal as the clocksignal.

[0015] By this, the information-processing unit executes variousinformation processing based on the clock signal.

[0016] As a power supply, a normal power supply such as a battery or aconstant-voltage regulated power supply such as a voltage regulator maybe used.

[0017] Also, the present invention is characterized by providing aninformation processing apparatus comprising: a first oscillating circuitthat generates a first clock signal by using oscillation and has a firstoscillation stability time, the first oscillation stability time being atime required for the first oscillating circuit becoming stable from abeginning of the oscillation of the first oscillating circuit; a secondoscillating circuit that starts oscillating concurrently with the firstoscillating circuit, generates a second clock signal by usingoscillation, and has a second oscillation stability time, the secondoscillation stability being a time required for the second oscillatingcircuit becoming stable from a beginning of the oscillation of thesecond oscillating circuit, and being longer than the first oscillationstability time; a switching circuit for, based on an elapsed time fromthe beginning of the oscillation, outputting either the first clocksignal or the second clock signal as the clock signal; and aninformation processing unit for, in synchronism with the clock signal,performing information processing.

[0018] By the above configuration, the first oscillating circuitgenerates the first clock signal and outputs it to the switchingcircuit.

[0019] The second oscillating circuit generates the second clock signaland outputs it to the switching circuit.

[0020] By this, the information-processing unit executes variousinformation processing based on the clock signal.

[0021] Also, the present invention is characterized by providing acontrol method for an information processing apparatus, the informationprocessing apparatus comprising: an information processing unit for,based on a clock signal, carrying out various information processingoperations; a first oscillating circuit that generates a first clocksignal and is able to operate until power supply voltage reaches a firstlowest operating voltage, a second oscillating circuit that generates asecond clock signal and is able to operate until the power supplyvoltage reaches a second lowest operating voltage that is higher thanthe first lowest operating voltage; a switching circuit for, based onthe power supply voltage, outputting either the first clock signal orthe second clock signal as the clock signal; and the control methodcomprising: determining power supply voltage; outputting by theswitching circuit the first clock signal as the clock signal when thepower supply voltage is equal to or higher than the first lowestoperating voltage and lower than the second lowest operating voltage;and outputting by the switching circuit the second clock signal as theclock signal when the power supply voltage is higher than the secondlowest operating voltage.

[0022] By the above configuration, during determining power supplyvoltage, power supply voltage is determined.

[0023] During outputting the first clock signal, when the power supplyvoltage determined during determining power supply voltage is equal toor higher than the first lowest operating voltage and lower than thesecond lowest operating voltage, the switching circuit outputs the firstclock signal as the clock signal.

[0024] During outputting the second clock signal, when the power supplyvoltage is equal to or higher than the second lowest operating voltage,the switching circuit outputs the second clock signal as the clocksignal.

[0025] Also, the present invention is characterized by providing acontrol program executed by an information processing apparatus, theinformation processing apparatus comprising: an information processingunit for, based on a clock signal, carrying out various informationprocessing operations; a first oscillating circuit that generates afirst clock signal and is able to operate until power supply voltagereaches a first lowest operating voltage, a second oscillating circuitthat generates a second clock signal and is able to operate until thepower supply voltage reaches a second lowest operating voltage that ishigher than the first lowest operating voltage; and a switching circuitfor, based on the power supply voltage, outputting either the firstclock signal or the second clock signal as the clock signal; and thecontrol program comprising the routines of: determining the power supplyvoltage; outputting to the switching circuit the first clock signal asthe clock signal when the power supply voltage is equal to or higherthan the first lowest operating voltage and is lower than the secondlowest operating voltage; and outputting to the switching circuit thesecond clock signal as the clock signal when the power supply voltage ishigher than the second lowest operating voltage.

[0026] By the above configuration, the control program makes theinformation processing apparatus determine power supply voltage, whenthe power supply voltage is equal to or higher than the first lowestoperating voltage and lower than the second lowest operating voltage,makes the switching circuit output the first clock signal as the clocksignal, and when the power supply voltage is equal to or higher than thesecond lowest operating voltage, makes the switching circuit output thesecond clock signal as the clock signal.

BRIEF DESCRIPTION OF THE DRAWINGS

[0027]FIG. 1 is a plan view that shows a configuration of a watch-typeinformation processing apparatus and a station of a first embodiment.

[0028]FIG. 2 is a section view taken on line A-A in FIG. 1.

[0029]FIG. 3 is a front view of a watch-type information processingapparatus according to an embodiment of the present invention.

[0030]FIG. 4 is a diagram that shows a state of the informationprocessing apparatus whose turning bezel is removed, FIG. 5 is a sectionview taken on line IV-IV in FIG. 3.

[0031]FIG. 6 is a diagram that shows the underside of the turning bezel.

[0032]FIG. 7 is a diagram that explains a relation between an opticalpattern made on the turning bezel and a first detection signal or asecond detection signal.

[0033]FIG. 8 is a schematic configuration block diagram of thewatch-type information processing apparatus.

[0034]FIG. 9 is a detailed configuration block diagram of the oscillatorunit in the information processing apparatus.

[0035]FIG. 10 is a detailed configuration diagram of the crystal quartzoscillating circuit in the oscillator unit.

[0036]FIG. 11 is a detailed configuration diagram of the CR oscillatingcircuit in the oscillator unit.

[0037]FIG. 12 is a detailed configuration diagram of the PLL oscillatingcircuit in the oscillator unit.

[0038]FIG. 13 is a detailed configuration block diagram of the voltagegenerating unit in the information processing apparatus.

[0039]FIG. 14 is a detailed configuration block diagram of the inputinformation-processing unit in the information processing apparatus.

[0040]FIG. 15 is a processing timing chart showing time keepingoperation and switching operation of the information processingapparatus.

[0041]FIG. 16 is a processing timing chart showing operation of theinformation processing apparatus when power supply voltage declines.

[0042]FIG. 17 is a schematic block diagram of a PLL oscillating circuitof the embodiment.

[0043]FIG. 18 is a detailed block diagram of a phase comparator and acharge pump that is connected to latter part of the PLL oscillatingcircuit.

[0044]FIG. 19 is a timing chart showing the operation of the phasecomparator and the charge pump.

[0045]FIG. 20 is an explanatory diagram of the LPF.

[0046]FIG. 21 is a detailed block diagram of the voltage controlledoscillator (VCO).

[0047]FIG. 22 is an explanatory diagram for the lockup time of the PLLoscillating circuit of the second embodiment.

[0048]FIG. 23 is an explanatory diagram for the lockup time of theconventional PLL oscillating circuit.

[0049]FIG. 24 is a schematic configuration block diagram of amodification of the second embodiment.

DETAILED DESCRIPTION

[0050] With reference to drawings, preferred embodiments of the presentinvention will be described below.

[1] First Embodiment

[0051] [1.1] Configuration of the First Embodiment

[0052] [1.1.1] Mechanical Configuration

[0053]FIG. 1 shows a plan view of a watch-type information processingapparatus and a station according to the first embodiment. In FIG. 1, awatch-type information processing apparatus 200 has a secondary batteryas a power source and receives power from the secondary battery, therebyable to function as a watch and an information processing apparatus. Inmore detail, the watch-type information processing apparatus 200, whenused normal way, is worn on a user's wrist, displays date and time on adisplay section 204, and has an information-processing function thatperiodically measures and stores biological information such as pulserate and heart rate by using sensor (not shown). The station 100 is adevice used for charging the secondary battery of the watch-typeinformation processing apparatus 200 and for data transferring with thewatch-type information processing apparatus 200. The station 100 has aconcave portion 101 which is slightly bigger than the body 201 and aband 202 of the watch-type information processing apparatus 200. Thewatch-type information processing apparatus 200 is embedded in theconcave portion 101.

[0054] The station 100 comprises various input units such as a chargestart button 1031 for starting the charging and a transfer start button1032 for starting the data transferring, and a display unit 104 forcarrying out various display.

[0055]FIG. 2 is a section view taken on line A-A in FIG. 1. As shown inFIG. 2, the underside of the body 201 of the watch-type informationprocessing apparatus 200 is closed with a back cover 212. The watch-typeinformation processing apparatus 200 is embedded in the station 100 in amanner by which the back cover 212 and the bottom of the concave portion101 face each other. In a space inside the back cover of the body 201 isa circuit board 221 and the secondary battery 220 which provides thecircuit on the circuit board 221 with power supply voltage. The backcover 212 has an opening which is closed by a cover glass 211. On thesurface of the inner part of the cover glass 211, a watch-side coil 210for data transferring and charging is placed.

[0056] On the other hand, at the bottom of the concave portion 101 ofthe station 100, there is space accommodating a circuit board 121. Theboard 121 is connected to the charge start button 103A, the transferstart button 103B, the display unit 104, and a primary battery (notshown). At the roof of the space is an opening which is closed with acover glass 111. Inside the cover glass, a station-side coil 110 isfixed. The station-side coil 110 faces the watch-side coil 210 of thebody through the cover glass 111 of the station 100 and the cover glass211 of the body.

[0057] In this way, in a case where the watch-typeinformation-processing apparatus 200 is placed in the station 100, thestation-side coil 110 is not in physically contact with the watch-sidecoil 210 because of the cover glasses 111 and 211. However, the coils110 and 210 are in electromagnetic contact with each other, because thecoils are placed in almost parallel.

[0058] The station-side coil 110 and the watch-side coil 210 are ofmagnetic coreless type in order to avoid magnetization of the watchmechanism section, weight increase of the watch, and exposure ofmagnetic metal. However, if the invention is applied to an electronicapparatus to which the above matters are not important, coils withmagnetic core may be used. However, when signal frequency provided tocoil is high enough, a coreless coil works well enough.

[0059]FIG. 3 is a front view of a watch-type information processingapparatus. On the front side (on near side of the drawing sheet) of thebody 201, a circle shaped turning bezel 202 is placed so that theturning bezel 202 can slide on the body 201. On the turning bezel 202,characters (such as alphabetic characters, Japanese syllabaries, and/ornumeric characters) are placed at regular intervals by printing.

[0060] Inside the turning bezel 202, a cover glass 203 is attached.Below the cover glass 203 (on the far side of the drawing sheet), thedisplay section 204 is fixed that displays information input to thewatch-type information processing apparatus 200. On the upper side ofthe display section 204, an indicator mark 209 is formed by printing orthe other method. The indicator mark 209 indicates one of the characterson the turning bezel 202. Around the body 201, a confirmation switch205, a delete switch 206, a sonant mark switch 207, and a starting pointswitch 208 are built. These switches may be built on the cover glass203.

[0061]FIG. 4 is a diagram that shows a state of the informationprocessing apparatus 200 whose turning bezel 202 is removed. FIG. 5 is asection view taken on line IV-IV in FIG. 4. As shown in FIGS. 4 and 5,on the body 201, a gutter 34 is formed along the circle. On the otherhand, as shown in FIG. 5, on the undersurface of the turning bezel 202is formed a protrusive line 46 that protrudes towards inner side of thebody. The protrusive line 46 is engaged to the gutter 34 in order to beable to slide. Between the right side of the turning bezel in FIG. 5 andthe body 201, an O-ring 47 is built in. The O-ring 47 prevents water andlight from entering the inner part of the watch-type informationprocessing apparatus 200.

[0062] As shown in FIG. 4, holes 31 a and 31 b are formed on the body201. In the holes 31 a and 31 b, a first sensor unit 32 and a secondsensor unit 33 are placed respectively. In this case, the first sensorunit 32 and the second sensor unit 33 are placed so that the anglebetween the line from the rotation center O of the turning bezel 202 tothe first sensor unit 32 and the line from the rotation center O of theturning bezel 202 to the second sensor unit 33 becomes θ1. Details ofthe angle θ1 will be described later.

[0063] The first sensor unit 32 is placed under (far side of the drawingsheet of FIG. 4) a character indicated by the indicator mark 209 (inFIG. 4, the character is “A”).

[0064] As shown in FIG. 5, on the undersurface of the turning bezel 202,optical pattern 41 is formed in a location that corresponds to characteron the turning bezel 202. Below the surface where the optical pattern 41is formed, a sensor cover glass 42 is attached to the body 201. Betweenthe body 201 and the sensor cover glass 42, a packing 43 is put in. Bythis, it is possible to prevent water and other stuff from enteringbelow the sensor cover glass 42.

[0065] Below the sensor cover glass 42, the first sensor unit 32 isplaced. The first sensor unit 32 comprises an light emitting diode (LED)44, a photodiode 45, a light blocking plate 44 a which is placed betweenthe LED 44 and the photodiode 45, and a base plate 48. The LED 44 emitsa first detection light L1 to the optical pattern 41. The photodiode 45receives reflected light. Based on the received first detection lightL1, the first sensor unit 32 generates a first detection signal A.

[0066] The second sensor unit 33 comprises an LED, and a photodiode, alight blocking plate, and a base plate, those components being similarto those of the first sensor unit 32. The LED emits a second detectionlight L2 to the optical pattern 41. The photodiode receives reflectedlight. Based on the received second detection light L2, the secondsensor unit 33 generates a second detection signal B.

[0067] Below the base plate 48 of the first sensor unit 32, a contactspring 49 is built. The contact spring 49 electrically connects thefirst sensor unit 32 and the second sensor unit 33 to a CPU of thewatch-type information processing apparatus 200. Instead of the contactspring 49, lead wires may be used.

[0068] In this way, the first detection signal and the second detectionsignal B are counted by an information processing unit 81 shown in FIG.14 (which is later described). By this, rotation angle and rotationdirection of the turning bezel 202 is determined.

[0069] [1.1.2] About Optical Pattern

[0070] Next, the optical pattern 41 will be described. FIG. 6 is adiagram that shows the underside of the turning bezel 202, the undersidefunctions as a reflective member. As shown in FIG. 6, on the undersideof the turning bezel 202, the optical pattern 41 is formed along thecircle line, the optical pattern 41 having an alternately repetitivepattern of an absorption region 41 a that absorbs light emitted by theLED 44 and a reflection region 41 b that reflects light emitted by theLED. In this case, a line segment that is from the rotation center O tothe middle of either an absorption region 41 a or a reflection region 41b makes an angle of θ2 with a line segment that is from the middle ofeither a neighboring reflection region 41 b or a neighboring absorptionregion 41 a to the rotation center O.

[0071] In this case, if the number of characters formed on the turningbezel 202 is n (n is an even number), θ2=360/n(°)

[0072] The first sensor unit 32, when a user turns the turning bezel202, alternately reads the absorption region 41 a and the reflectionregion 41 b of the optical pattern shown in the part (a) of FIG. 7,thereby is able to generate the first detection signal. A which hasapproximate sinewave form as shown in the part (c) of FIG. 7.

[0073] In the same way, the second sensor unit 33 generates the seconddetection signal B which has approximate sinewave form shown in the part(c) of FIG. 7.

[0074] In the above case, the absorption region 41 a, the reflectionregion 41 b, the first sensor unit 32, and the second sensor unit 33 areplaced so that the phase difference becomes a quarter of the wavelengthas described later.

[0075] [1.1.3] Arrangement of Sensor Unit

[0076] Next, the angle θ2 between the first sensor unit 32 and thesecond sensor unit 33 will be described.

[0077] In this embodiment, the first sensor unit 32 and the secondsensor unit 33 are placed so that the angle θ1 equals θ2 plus η2/2. Bythis, when a user turns the turning bezel 202, a phase difference of aquarter of the wave length is produced between the first detectionsignal A generated by the first sensor unit 32 and the second detectionsignal B generated by the second sensor unit 33.

[0078] As shown in FIG. 7, when a user turns the turning bezel 202 in aclockwise direction, the second detection signal has an advanced phaseof one quarter of the wavelength to the first detection signal. On theother hand, when a user turns the turning bezel 202 in acounterclockwise direction, the second detection signal has a phasedelay of one quarter of the wavelength to the first detection signal. Bydetecting these phase advance and delay, it becomes possible todetermine direction of rotation of the turning bezel 202 as describedlater.

[0079] [1.1.4] Schematic Configuration

[0080] Next, with reference to FIG. 8, schematic configuration of thewatch-type information processing apparatus 200 will be described. Onthe circuit board 221 shown in FIG. 2, a micro-processing unit (MPU)251, an oscillating unit 252, a charging and communication unit 253, aflash memory 254, an LCD driver 255, an LCD 256, an input outputinterface unit 257, a voltage generating unit 258, a voltage determiningunit 259, a RAM 260, an input information processing unit 261 areplaced, and a bus 262 is formed to connect the above components. Theoutput voltage of the secondary battery 220 is provided to the voltagegenerator 258 and the voltage determining unit 259.

[0081] The micro-processing unit 251 controls the entire watch-typeinformation processing apparatus 200. When performing this control, themicro processing unit 251 outputs control signals CNT1, CNT2, CNT3, andCNT4 to the oscillating unit 252.

[0082] The oscillating unit 252, based on the control signals CNT1 toCNT4, generates and outputs clock signals CLK11 and CLK12.

[0083] The charging and communication unit 253 is provided with electricpower from the station 100 via the watch-side coil 210, and provides acharging current to the secondary battery 220. The charging andcommunication unit 253 also performs data transmission and receptionwith the station 100 via the watch-side coil 210.

[0084] The secondary battery 220 stores the charging current provided bythe charging and communication unit 253. The battery voltage is providedto various units as power supply voltage for operation.

[0085] The flash memory 254 is a non-volatile memory that storesdisplaying pattern data items for displaying various characters, andfunctions as a character generator.

[0086] The LCD driver 255, under controls of the micro-processing unit251, displays various data items on the display 256.

[0087] The input output interface unit 257 determines operatingconditions of the confirmation switch 205, the delete switch 206, thesonant mark switch 207, and the starting point switch 208, and performsinterface operation between the switches and the micro-processing unit251.

[0088] The voltage generating unit 258 receives the power supply voltageVCC from the secondary battery 220 and provides power supply voltageVCC1 for a quartz crystal oscillating circuit and system power supplyvoltage VCC2.

[0089] The voltage determining unit 259 determines voltage of the powersupply voltage VCC of the secondary battery.

[0090] The RAM 260 temporarily stores various data items.

[0091] The input information-processing unit 261 receives data itemsinput with operation of the bezel 202 and performs data inputprocessing. The data input processing is to provide the input data itemsto the MPU 251.

[0092] Next, explanations will be given of detailed configurations ofthe oscillating unit 252, the voltage generating unit 258, and the inputinformation-processing unit 261.

[0093]FIG. 9 is a detailed configuration block diagram of theoscillating unit. The oscillating unit 252 comprises a quartz crystaloscillating circuit 51, a CR oscillating circuit 52, a PLL oscillatingcircuit 53, and a selector 54.

[0094] The quartz crystal oscillating circuit 51 is a low-speedoscillating circuit and, by receiving the control signal CNT2 and powersupply voltage VCC1 for the quartz crystal oscillating circuit, outputsa clock signal CLK1 having low frequency (for example 32 kHz) for timekeeping.

[0095] The CR oscillating circuit 52 is a first high-speed oscillatingcircuit, based on the control signal CNT3, outputs a clock signal CLK11having high frequency (for example from 1 MHz to 8 MHz) for informationprocessing.

[0096] The PLL oscillating circuit 53 is a second high-speed oscillatingcircuit, based on the control signal CNT4, outputs a clock signal CLK12having high frequency (for example from 4 MHz to 16 MHz) for informationprocessing.

[0097] The selector 54, based on the control signal CNT1 from theinformation processing unit 81 (which is described later), selectseither the CR oscillating circuit 52 or the PLL oscillating circuit 53and outputs the output signal of the selected circuit as a clock signalCLK2.

[0098] In the above case, the clock signal CLK1 from the quartz crystaloscillating circuit 51 is used for time keeping, and the clock signalCLK2 is used for information processing by the information processingunit 81 (which is described later).

[0099] Here, explanation will be given of the configurations of thequartz crystal oscillating circuit 51, the CR oscillating circuit 52,and the PLL oscillating circuit 53.

[0100] The configuration of the quartz crystal oscillating circuit 51 isshown in FIG. 10. The quartz crystal oscillating circuit 51 comprises afirst inverter circuit 51E. Between the input terminal and the outputterminal of the inverter circuit 51 are connected a quartz oscillator51A and a resistor 51B in parallel with the first inverter circuit 51E.The quartz oscillator 51A has an oscillating frequency of 32 kHz. Theinput terminal of the first inverter circuit 51E is connected to thelower voltage side power source (GND) via a capacitor 51C. The outputterminal of the first inverter circuit 51E is connected to the lowervoltage side power source (GND) via a capacitor 51D. A second invertercircuit 51F amplifies the output signal of the first inverter circuit51E and outputs the clock signal CLK1 having a frequency of 32 kHz.

[0101] The CR oscillating circuit 52 is shown in FIG. 11. The CRoscillating circuit 52 comprises a first inverter circuit 52B, a secondinverter circuit 52C, and a third inverter circuit 52E which areconnected in cascade. Between the input terminal and the output terminalof the inverter 52B, a feedback resistor 52A is connected. Between theinput terminal of the inverter 52B and the output terminal of theinverter 52C, a capacitor 52D is connected. The third inverter circuit52E receives the oscillating signal from the second inverter circuit52C, amplifies it, and outputs it as clock signal CLK11.

[0102] The PLL oscillating circuit 53 is shown in FIG. 12. The PLLoscillating circuit 53 has a looping formation circuit which is formedby a phase comparator 53A, a charge pump 53B, a low pass filter (LPF)53C, a voltage controlled oscillator (VCO) 53D, and a divider 53E. Thephase comparator 53A compares a phase of the clock signal CLK1 and aphase of the output signal of the divider 53E, and outputs an outputsignal corresponding to phase difference between them. The charge pump53B introduces a current into the LPF 53C in response to the outputsignal of the phase comparator 53A. The LPF 53C selects only lowerfrequency component of the output signal of the charge pump 53B, andoutputs it as a voltage control signal. The VCO 53D oscillates in afrequency corresponding to the voltage control signal output from theLPF 53C, and outputs the clock signal CLK12. The divider 53E divides thefrequency of the clock signal CLK12 into an Nth of its frequency.

[0103] In the above configuration, when there is a phase differencebetween the incoming clock signal CLK1 and the output signal of thedivider 53E, synchronization establishment is carried so as to reducethe phase difference and make the output signal of the divider 53Ephase-locked with the clock signal CLK1. When the synchronization isestablished and a state of the PLL oscillating circuit reaches asynchronization maintained state where the output signal of the divider53E is kept to be in phase-locked with the clock CLK1, the phasecomparator 53A outputs a lock-up signal CNT6 having the “H” levelindicating the above information.

[0104] Here, advantages and disadvantages of CR oscillating circuits andPLL oscillating circuits will be explained.

[0105] CR oscillating circuits require about four time more powerconsumption than PLL oscillating circuits do, but the waiting time forconstant oscillation of CR oscillating circuits is shorter than that ofPLL oscillating circuits. For example, the waiting time for constantoscillation of CR oscillating circuits is about 5 msec. CR oscillatingcircuits, when used under its upper limited frequency of 1 MHz, isoperable at a voltage that is lower than a lower limited voltage for theoperation of PLL oscillating circuits (for example until as low as 1.5V). Hereinafter, for the sake of convenience, a waiting time forconstant oscillation of CR oscillating circuits is referred to as afirst oscillation stability time, and a lowest limited operating voltageas a first lowest operating voltage.

[0106] On the other hand, PLL oscillating circuits are able to oscillateuntil at a considerably high frequency with low power consumption.However, PLL oscillating circuits have long waiting time for constantoscillation (for example 50 msec), and its lowest operating limitedvoltage is high (for example 2 V). Hereinafter, for the sake ofconvenience, a waiting time for constant oscillation of PLL oscillatingcircuits is referred to as a second oscillation stability time, and alowest limited operating voltage as a second lowest operating voltage.

[0107] Therefore, CR oscillating circuits and PLL oscillating circuitshave their merits and demerits. In this embodiment, by combiningadvantages of each oscillating circuits, a high-speed oscillatingcircuit with low power consumption, low operating voltage, and shortwaiting time for constant oscillation is achieved.

[0108] The voltage generating unit 258, as shown in FIG. 13, comprises afirst constant voltage circuit 258A and a second constant voltagecircuit 258B. The first constant voltage circuit 258A generates powersupply voltage VCC1 for the quartz crystal oscillating circuit from thepower supply voltage VCC. The second constant voltage circuit 258B iscontrolled by the control signal CNT5 and generates the system powersupply voltage VCC2 from the power supply voltage VCC.

[0109] Next, with reference to FIG. 14, detail of the inputinformation-processing unit 261 will be described. The input informationprocessing unit 261 comprises the information processing unit 81 whichhas a counter 813 for counting the number of pulses of the firstdetection signal A from the first sensor unit 32 and a counter 814 forcounting the number of pulses of the second detection signal B from thesecond sensor unit 33. The first detection signal A and the seconddetection signal B are changed into detection pulse signals PA and PB bywaveform shapers 811 and 812 respectively. These pulses are input to thecounters 813 and 814. The input information-processing unit 261 alsocomprises a judging unit 815 for determining direction of rotational andlocation of the turning bezel 202 based on the counted values of thecounters 813 and 814 and detection pulse signals PA and PB. In thiscase, the judging unit 815 judges direction of rotation based on, forexample, level (“H” or “L”) of the detection pulse signal PB at positiveedge of the detection pulse signal PA.

[0110] The input information processing unit 261, based on the firstdetection signal A generated by the first sensor unit 32 and the seconddetection signal B generated by the second sensor unit 33, generatesinformation data and stores the information data confirmed by a userinto the RAM 260.

[0111] In the above case, the information-processing unit 81, byreferring to information table on the flash memory 254 generates aninformation signal. The flash memory 254 stores conversion tables: oneof the conversion table is used for converting the output data of thejudging unit 815 into a code of character designated by the turningbezel, and one other conversion tables is used for converting the outputof the judging unit 815 into a code of image data of the characterdesignated by the turning bezel 202. The flash memory also storesinformation items corresponding to a location of the turning bezel 202,Based on the information signal, and by using the character generator inthe flash memory 254, the LCD driver 255 displays characters and otherinformation on the LCD 256.

[0112] In addition, the information processing unit 81 can processfollowing processing.

[0113] For example, document files made on other personal computer maybe transmitted to the apparatus via the charging and communication unit253 and the station 100, then displayed on the LCD 256.

[0114] When a simple operating system (OS) is installed in theinformation processing unit 81, simple application programs can be madefor the OS. Creatable application programs are for example schedulemanaging program and address data managing program. Further, importingand exporting data such as scheduling data and address data from otherpersonal computer can be possible. Data processing such as dataaddition, data deletion, or data sorting can be possible.

[0115] Next, roles of the starting point switch 208, the confirmationswitch 205, the delete switch 206, and the sonant mark switch 207 willbe described.

[0116] The starting point switch 208 is a switch that changes thewatch-type information processing apparatus into a state of aninformation input. When the switch 208 is turned on, the counter for thenumber of pulses in the unit 81 is reset to “0” and the judging unit 815starts measuring rotation angle and direction of the turning bezel 202using the first sensor unit 32 and the second sensor unit 33.

[0117] The confirmation switch 205 and the delete switch 206 are usedfor confirmation and deletion of the information items generated by theinformation-processing unit 82.

[0118] The sonant mark switch 207 is used for adding a sonant mark whenthe generated information item by the information-processing unit 81 isa Japanese syllabary and requires a sonant mark. When the generatedcharacter is an alphabetic character, the switch 207 is used forswitching the character between a capital letter and a small letter.

[0119] The information items generated by the information-processingunit 81 are not limited to character. Instruction codes for such as linefeed and mode switching (for example, between time display mode andcharacter input mode) may also be generated by the informationprocessing unit 81. In this case, the information table on the flashmemory 254 stores instruction codes for such as line feed and modeswitching with correspondence with location of the turning bezel 202.Based on location of the turning bezel 202, the information-processingunit 81 generates instruction codes.

[0120] [1.2] Operation of the Information Processing Unit and theOscillating Circuit

[0121] Here, by paying an attention to operations of theinformation-processing unit 81 and the oscillating circuits 51, 51, and53, an explanation will be given. FIG. 15 is a processing timing chartduring time keeping operation and switching operation to informationprocessing.

[0122] [1.2.1] Operation During Time Keeping

[0123] In an initial state, the control signal CNT2 output from themicro-processing unit 251 has the “H” level. The quartz crystaloscillating circuit 51 is in an operating state and outputs the clocksignal CLK1 to the information-processing unit 81. The control signalCNT1 has the “L” level. Thereby, the selector 54 selects the CRoscillating circuit 52.

[0124] By this, the information-processing unit 81, based on the clocksignal CLK1, performs time keeping operation and displays time on thedisplay unit 104.

[0125] While the information processing unit 81 displays time, thecontrol signals CNT3 and CNT4 have the “L” level, and the CR oscillatingcircuit 52 and the PLL oscillating circuit 53 are in an inoperativestate or a standby state.

[0126] [1.2.2] Shift to the Information Processing Operation

[0127] At time t1 in FIG. 15, the starting point switch 208 is used anda starting point signal becomes the “H” level. By this, theinformation-processing unit 81 is switched from time keeping operationto information processing operation.

[0128] By this, the micro processing unit 251 makes the control signalsCNT3 and CNT4 to the “H” level so that the CR oscillating circuit 52 andthe PLL oscillating circuit 53 start oscillating. In this case, an earlystage oscillation stabilization frequency of the CR oscillating circuit52 is about 1 MHz, and an early stage oscillation stabilizationfrequency of the PLL oscillating circuit 53 is about 4 MHz.

[0129] By this, the state of the CR oscillating circuit 52 graduallyshifts to an oscillation stable state. In the above case, at time t2which is 5 msec after beginning of oscillation, the CR oscillatingcircuit 52 is in an oscillation stable state. The information-processingunit 81 starts its operation using the clock signal CLK12 as the clocksignal CLK2.

[0130] On the other hand, at time t2 (a first oscillation stability timeelapsed point: 5 msec elapsed point), the PLL oscillating circuit 53 isin an oscillation non-stable state.

[0131] Subsequently, oscillation frequency of the CR oscillating circuit52 gradually increases, resulting in around 4 MHz.

[0132] At time t3 (a second oscillation stability time elapsed point)where 50 msec has elapsed since the time t2, the PLL oscillating circuit53 also enters an oscillation stable state, where oscillation frequencyis also around 4 MHz.

[0133] Therefore, the micro-processing unit 251 makes the control signalto the “H” level and changes the selection of the selector 54 to the PLLoscillating circuit 53.

[0134] After this, the information-processing unit 81 operates using theclock signal CLK 12 as the clock CLK2.

[0135] Further, at time t4, the micro-processing unit 251 makes thecontrol signal CNT4 to the “L” level and stops oscillation of the CRcircuit 52.

[0136] Subsequently, the micro-processing unit 251 gradually raisesoscillation frequency of the PLL oscillating circuit 53. By this, thewatch-type information apparatus works at a desired high-speed frequency(for example 12 MHz, but in this embodiment 16 MHz).

[0137] [1.2.3] Operation During Declining of the Power Supply Voltage

[0138]FIG. 16 is a processing timing chart when power supply voltagedeclines. The information-processing unit 81, in a case whereinformation processing is performed in a steady state, uses the clocksignal CLK12 which corresponds to oscillation frequency of the PLLoscillating circuit 53 as the clock signal CLK2 as mentioned above.

[0139] However, there can be a case where the declining of the powersupply voltage stops the operation of the PLL oscillating circuit 53.That is, when the power supply voltage becomes lower than the secondlowest operating voltage, the PLL oscillating circuit 53 cannot operateproperly.

[0140] Therefore, the MPU 251, based on the result of the voltagedetermining unit 259, when the power supply voltage declines to avoltage which is higher or equal to the first lowest operating voltageand lower than the second lowest operating voltage, selects the CRoscillating circuit 52. When the power supply voltage further declinesto lower than the first lowest operating voltage, theinformation-processing unit 81 is stopped.

[0141] It is assumed that, in this case, the voltage determining unit259 determines voltage, for example, every hour on the hour.

[0142] To be concrete, at time t1 in FIG. 16, the voltage determiningunit 259 determines voltage of the secondary battery 220. When thevoltage reaches a prescribed switching voltage (for example, in theabove case, about 2.2 V), the micro-processing unit 251 starts the CRoscillating circuit 52 by making the control signal CNT4 to the “H”level at time t2.

[0143] The micro-processing unit 251 gradually lowers oscillationfrequency of the PLL oscillating circuit 53 to around 4 MHz.

[0144] At time t3, oscillation frequency of the CR oscillating circuit52 has already reached 4 MHz. Therefore, the micro-processing unit 251makes the control signal CNT1 to the “L” level and changes the selectionof the selector 54 to the CR oscillating circuit 52.

[0145] Therefore, after this, the information-processing unit 81operates using the clock signal CLK11 as the clock CLK2. It becomespossible to perform information processing operation until power supplyvoltage declines to around 1.5 V which is the lowest operating voltageof the CR oscillating circuit 52.

[0146] Further, at time t4, the micro-processing unit 251 makes thecontrol signal CNT3 to the “L” level and stops oscillation of the PLLcircuit 53.

[0147] Subsequently, the voltage determining unit 259 measures voltageof the secondary battery 220. When the voltage of the secondary battery220 reaches around 1.5 V which is the lowest operating voltage of the CRoscillating circuit 52, the micro-processing unit 251 notifies this tothe user. By this, the micro processing unit 251 urges the user tocharge secondary battery or change battery.

[0148] Further, at time t5 when the voltage determining unit 259measures voltage of the secondary battery 220, if power supply voltageis lower than 1.5 V, the MPU 251 makes the control signal CNT4 to the“L” level and stops oscillation of the CR oscillating circuit 52 at timet6.

[0149] As a result, the information processing unit 81 stops informationprocessing operation and continues to performs time keeping operationuntil power supply voltage becomes the lowest operating voltage of thequartz crystal oscillating circuit 51 of around 1 V.

[0150] [1.3] Effect of the First Embodiment

[0151] As described above, according to the first embodiment of thepresent invention, by using CR oscillating circuit and PLL oscillatingcircuit selectively, it becomes possible to provide a lowpower-consumption, short waiting-time for stable oscillation, lowoperating voltage information-processing apparatus.

[0152] In addition, so far, when using software which places asignificant burden on the overall performance of the operation such asbrowser, high-speed clock is required in order to use it withoutfrustration. In this embodiment, by using CR oscillating circuit, whenbattery voltage declines and PLL oscillating circuit becomes unable tooperates, although speed of display becomes slow, displaying is notimpossible, and even in very low voltage it becomes possible to continueto display.

[0153] In addition, it becomes possible to start application softwarefrom time keeping operation.

[0154] Further, when battery voltage declines considerably, it ispossible to operate information-processing unit, thus enabling usingapplication software in a very low battery voltage.

[2] Second Embodiment

[0155] As described in the explanation for the first embodiment above,PLL oscillating circuit operates at low power consumption even at highfrequency, but requires long waiting time for stable oscillation.

[0156] In order to avoid this, following measures are used inconventional PLL oscillating circuit.

[0157] (1) Using two low pass filters (LPF); when starting to use PLLoscillating circuit LPF with small time constant is used, and whenoscillation becomes stable LPF with large time constant is used.

[0158] (2) Using two low pass filters (LPF); when one LPF is used, theother LPF is prepared to lock up with other frequency.

[0159] (3) When PLL oscillating circuit has a charge pump foranalog/digital conversion of the output signal of phase comparator,increasing a control current for charge pump at starting up PLLoscillating circuit.

[0160] Measures (1) and (2) cannot make lock-up time to zero, andmeasure (3) makes device configuration complicated and circuit bigger.

[0161] Accordingly, a second embodiment provides shorter lock-up timethan the PLL oscillating circuit of the first embodiment does, enablingto shift to higher frequency operation in information processingoperation.

[0162] In the following explanation, configuration except PLLoscillating circuit is the same as that of the first embodiment, somainly PLL oscillating circuit will be described.

[0163] [2.1] Schematic Configuration of the PLL Oscillating Circuit

[0164] A PLL oscillating circuit 53, as shown in FIG. 17, comprises aphase comparator 53A, a charge pump 53B, an LPF 53C, a voltagecontrolled oscillator (VCO) 53D, a D/A converter 53F, a divider 53E, anA/D converter 53G, and an adder 53H.

[0165] The phase comparator 53A compares phase of the clock signal CLK1and phase of the output signal of the divider 53E and outputs a digitaloutput signal that corresponds to phase difference.

[0166] The charge pump 53B, based on the output signal of the phasecomparator 53A, outputs a difference voltage that is proportional to thephase difference (frequency difference) of the clock signal CLK1 and acomparison clock signal CLK12/N.

[0167] The LPF 53C passes only low frequency component of the outputsignal of the charge pump 53B and outputs it as a voltage control signalSCV1.

[0168] The VCO 53D, based on the voltage control signal SCV output fromthe adder 53H, controls oscillation frequency of the clock signal CLK12and outputs it to the divider 53E.

[0169] The D/A converter 53F converts a digital signal from theinformation-processing unit 81 into an offset voltage signal SCV2. Theadder 53H adds the voltage control signal SCV1 to the clock controlsignal CLK12 to generates the voltage control signal SCV.

[0170] The divider 53E divides frequency of the clock signal CLK12 intoan Nth of its frequency and outputs it to the phase comparator 53A as acomparison clock signal CLK12/N.

[0171] The A/D converter 53G A/D converts the output voltage of the LPF53C into digital data indicating the output voltage and outputs it tothe information-processing unit 81 when the PLL oscillating circuit islocked during examination.

[0172] [2.2] Detailed Configuration of the PLL Oscillating Circuit

[0173] [2.2.1] Phase Comparator and Charge Pump

[0174]FIG. 18 is a detailed block diagram of a phase comparator and acharge pump that is connected to latter part of the PLL oscillatingcircuit.

[0175] Circuit configurations of the phase comparator 53A and the chargepump 53B will not described in detail since they are widely known. Withreference to a timing chart of FIG. 19, operations of these two circuitswill be described.

[0176] In the timing chart of the FIG. 19, an output signal U becomesthe “L” level when the phase of the comparison clock signal CLK12/N isadvanced to that of the clock signal CLK1 or when the frequency of theclock signal CLK12/N is higher than that of the clock signal CLK1. Thecomparison clock signal CLK12/N is a clock signal obtained by frequencydividing of the clock signal CLK12.

[0177] The output signal D becomes the “L” level when the phase of thecomparison clock signal CLK12/N is delayed to that of the clock signalCLK1 or when the frequency of the clock signal CLK12/N is lower thanthat of the clock signal CLK1.

[0178] When the phase of the comparison clock signal CLK12/N is equalsto the phase of the clock signal CLK1 at the rising timing, the bothoutput signals U and D becomes the “H” level. This state corresponds toa so-called locked state of the PLL oscillating circuit 53.

[0179] At this state, both a p-channel transistor and an n-channel MOStransistor that comprise the charge pump 53B becomes the OFF state, andthe output of the charge pump 53B is put in a high impedance state.

[0180] On the other hand, at time t1 and t2 as shown in a timing chartin FIG. 19, in a case where the phase of the comparison clock signalCLK12/N is advanced to the phase of the clock CLK1, or where thefrequency of the clock signal CLK12 is higher than that of the clocksignal CLK1, the output signal U becomes the “L” level during the timeinterval between the negative edge of the clock signal CLK12/N and thenegative edge of the clock signal CLK1. The time interval isproportional to the phase difference or the frequency difference. Atthis time, the output signal D remains the “H” level.

[0181] In the same way, at time t3 and t4 in FIG. 19, in a case wherethe phase of the comparison clock signal CLK12/N is delayed to the phaseof the clock CLK1, or where the frequency of the clock signal CLK12 islower than that of the clock signal CLK1, the output signal D becomesthe “L” level during a time period corresponding to the phase differenceor the frequency difference. At this time, the output signal U remainsthe “H” level.

[0182] When these output signals U and D is output from the phasecomparator 53A to the charge pump 53B, a p-channel transistor becomes ONonly while the output signal U has the “L” level, and an n-channel MOStransistor becomes ON only while the output signal D has the “L” level.

[0183] Therefore, the LPF 53C that is connected to following stage ofthe charge pump 53B outputs a direct current voltage corresponding tothe phase difference (frequency difference) between the clock signalCLK1 and the comparison clock signal CLK12/N (see FIG. 19).

[0184] The above description is about CMOS configured phase comparator.However, the above description may be applied to a bipolar configuredphase comparator.

[0185] [2.2.2] LPF

[0186]FIG. 20 shows a detailed configuration of the LPF, and equationsof natural angular frequency and dumping factor of the LPF. The LPF 53Cshown in FIG. 20 is a so-called lag-lead filter, so the LPF 53C is aconventional LPF. From a viewpoint of operating speed, the LPF 53C isworse than an active filter with an amplifier, but has enough usefulnesswhen configured in CMOS circuit. When PLL IC is configured with an LPFof CMOS circuit, lockup time can be reduced to around 10 msec.

[0187] In the above case, the natural angular frequency ωn and thedumping factor ζ are shown as follows:

ωn=✓{K _(p) ·K _(v)/(T ₁ +T ₂)·N}

ζ=ωn/2·(T ₂ +N/K _(p) ·K _(v))

[0188] Variables in the above equations are as follows:

[0189] K_(P): gain constant of the phase comparator (V/rad)

[0190] K_(V): gain constant of the voltage controlled oscillator (rad/sec/V)

[0191] N : divisor of the divider

[0192] [2.2.3] Voltage Controlled Oscillator

[0193]FIG. 21 shows a detailed configuration of voltage controlledoscillator constructed with CMOS. Since the circuit configuration of thevoltage controlled oscillator in FIG. 21 is widely known, explanation ofits configuration will be omitted, and only operation will be described.

[0194] The voltage controlled oscillator 53D is constructed with CMOS,so input impedance is high and the degree of design freedom of the LPF53C, the preceding circuit, increases.

[0195] In FIG. 21, when the control signal SC has the “H” level, thep-channel transistor P3 becomes OFF, thus enabling to stop oscillation.

[0196] When the control signal SC has the “L” level, the voltagecontrolled oscillator 53D becomes operating state, and since ann-channel transistor N1 is constructed in a source followerconfiguration, if a resistor R1 has high resistance enough, the draincurrent of the n-channel transistor N1 changes in linear relation withthe voltage control signal SCV.

[0197] Therefore, currents of the p-channel MOS transistors P1 and P2change in the same manner. As a result, drain currents of the p-channelMOS transistors P1 and P2 changes in linear relation with the voltagecontrol signal SCV.

[0198] On the other hand, gates G1 and G2 construct a flip-flap circuit,and a p-channel transistor P4, an n-channel transistor N2, a p-channeltransistor P5, and an n-channel transistor N3 work as switches.

[0199] When the output of the gate G1 has the “L” level, the output ifthe gate G2 has the “H” level, the p-channel transistor P5 and then-channel transistor N2 are in ON state, and the p-channel transistor P4and the n-channel transistor N3 are in OFF state.

[0200] Therefore, the input of the inverter INV becomes the lower sidepower supply voltage VSS, and electrical potential at the input terminalof the inverter INV5 rises because the capacitor C1 is charged by draincurrent of the p-channel transistors P2 and P5. Further, when outputsignal levels of the inverter INV5 to INV8 is reversed, outputs of thegate G1 and G2 that comprise a flipflap circuit are reversed.

[0201] Next, output of the gate G1 becomes the “H” level, output of thegate G2 becomes the “L” level, the p-channel transistor P5 and theN-channel transistor N2 become to OFF state, and the p-channeltransistor P4 and the n-channel transistor N3 become to ON state.Therefore, the capacitor C1 is charged by drain current of the p-channeltransistor P2 and P4. Then electrical potential at the input terminal ofthe inverter INV1 rises. Then, the output level of the inverters INV1 toINV4 is reversed. The same operation repeats after this.

[0202] In this case, the charging current of the capacitor C1 can becontrolled by voltage of the voltage control signal SCV. Therefore,frequency of the clock signal CLK12 is changeable.

[0203] [2.3] Operation of the Information Processing Unit and theOscillating Circuit

[0204] Here, operations of the information-processing unit 81, the CRoscillating circuit 52, and a PLL oscillating circuit 53 will bedescribed.

[0205] [2.3.1] Operation During Keeping Time

[0206] When the information-processing unit 81 displays time, asmentioned above for the first embodiment, the PLL oscillating circuit 53is in an inoperative state or a standby state under a control of themicro processing unit 259.

[0207] By this, the information-processing unit 81, based on the clocksignal CLK1, carries out time keeping operation and displays time on thedisplay unit 204.

[0208] [2.3.2] Shift to the Information Processing Operation

[0209] When the operation of the information processing unit 81 isswitched from time keeping operation to information processingoperation, the micro processing unit 259 starts oscillation of the PLLoscillating circuit 53 as in the case of the first embodiment.

[0210] In this case, the micro processing unit 259 sets an outputvoltage data stored in a register (not shown) or a non-volatile memoryof flash memory 254 corresponding to an output voltage of the LPF 53C,which output voltage is voltage of during a pre-conducted examinationand is voltage when the PLL oscillating circuit 53 is locked.

[0211] By this, the D/A converter 53F generates an offset voltage signalSCV2 that corresponds to an output voltage of the LPF 53C at apre-conducted examination. The offset voltage signal SCV2 is supplied tothe VCO 53D via the adder 53H. As a result, the VCO 53D startsoscillation at a frequency which nearly equals to the frequency at whichthe PLL oscillating circuit 53 is in lock up state.

[0212] On the other hand, the phase comparator 53A compares the phase ofthe clock signal CLK1 and the phase of the output signal the divider 53Eand outputs a (digital) output signal corresponding to the phasedifference between the above two signals to the charge pump 53B.

[0213] The charge pump 53B, based on the output signal of the phasecomparator 53A, outputs a difference voltage proportional to the phasedifference (frequency difference) between the clock signal CLK1 and thecomparison clock signal CLK12/N to the LPF 53C.

[0214] The LPF 53C passes lower component of the output signal of thecharge pump 53B and outputs it as the voltage control signal SCV1.

[0215] As a result, the input terminal of the voltage controlledoscillator (VCO) 53D receives the voltage control signal SCV which isproduced by s applying the offset voltage signal SCV2 on the voltagecontrol signal SCV1, the clock signal CLK12 having a frequencycorresponding to the voltage control signal SCV is generated, and theclock signal CLK12 is output to the information processing unit 81 andthe divider 53E.

[0216] The divider 53E divides the clock signal CLK12 output by thevoltage controlled oscillator 53D and outputs the divided signal as thecomparison clock signal CLK12/N to the phase comparator 53A. Thus,frequency of the clock signal CLK12 output by the voltage controlledoscillator 53D is locked in a desired frequency.

[0217] [2.4] Effect of the Second Embodiment

[0218] As described above, according to the second embodiment, at thebeginning of the operation of the PLL oscillating circuit 53, since theinput terminal of the voltage controlled oscillator (VCO) 53D receivesthe voltage control signal which is produced by applying the offsetvoltage signal SCV2 on the voltage control signal SCV 1, lockup time TRUof this embodiment (10 msec as shown in FIG. 22) becomes shorter thanlockup time of conventional PLL oscillating circuit (50 msec as shown inFIG. 23).

[0219] Therefore, compared to conventional way, it is possible toquickly start information processing operation. Further, from aviewpoint of control program, it is possible to omit waiting timeroutine that holds operation until the PLL oscillating circuit becomesstable, thereby enabling to ease software development.

[0220] Further, it is possible to improve response in various operationof the information processing apparatus.

[0221] [2.5] Modifications of the Second Embodiment

[0222] [2.5.1] First Modification

[0223] In the above description, the A/D converter 53G determinesvoltage of the LPF 53C when the PLL oscillating circuit 53 is lockedduring examination conducted in advance. Then the A/D converter 53G A/Dconverts the output voltage data that corresponds to this voltage andoutputs it to the CPU. However, it is possible to configure as follows.At a prescribed timing (on every predetermined hour, for example), thecontrol voltage input to the voltage controlled oscillator when the PLLoscillating circuit is locked up is A/D converted and set as a newoutput voltage data, thus, correcting the offset voltage in real-time.

[0224] By this, it is possible to set an offset voltage based on thenewest data, to remove errors of environmental factor such astemperature change, and to reach the lock up state more quickly.

[0225] [2.5.2] Second Modification

[0226] In the above description, D/A converter is used for generatingthe offset voltage signal SCV2. However, as shown in FIG. 24, it ispossible to generate a desired offset voltage signal SCV2 by using anexternally attached ladder-resistor 53J and selecting a tap location bythe selector 53I.

[0227] In addition, if a prescribed voltage is necessary as an offsetvoltage, it is possible to omit the selector 53I from the aboveconfiguration.

[3] Modifications of the Embodiments

[0228] [3.1] First Modification

[0229] In the above description, when a prescribed oscillation stabletime has passed, oscillating circuit in use is switched from CRoscillating circuit to PLL oscillating circuit. However, this switchingmay be carried out based on a signal indicating that PLL oscillatingcircuit has locked up (in the above-mentioned embodiment, the controlsignal CNT6 having “H” level).

[0230] [3.2] Second Modification

[0231] In the above description, for a first oscillating circuit, anexplanation is given only of a case of a CR oscillating circuit.However, it is possible to use a configuration that comprises a quartzoscillator circuit or a ceramic oscillating circuit on the assumptionthat it is used until the oscillation of the PLL oscillating circuitbecomes stable.

[0232] [3.3] Third Modification

[0233] In the above description, an explanation is given only of awatch-type information processing apparatus. However, if an informationprocessing apparatus is a twin-clock type information processingapparatus, it is possible to apply the present invention to a personaldigital assistant (PDA), a portable information processing apparatussuch as a note book type personal computer, or especially a informationprocessing apparatus using a secondary battery.

[0234] [3.4] Fourth Modification

[0235] In the above explanation, oscillations of CR oscillating circuitand PLL oscillating circuit are started at the same time. However, it ispossible to start CR oscillating circuit first and then start PLLoscillating circuit. In this case, from the oscillation of the CRbecomes stable to the oscillation of the PLL oscillating circuit becomesstable, the output signal of the CR oscillating circuit is used. Afterthe oscillation of the PLL oscillating circuit becomes stable, theoutput signal of the PLL oscillating signal is used.

[0236] [3.5] Fiftrh Modification

[0237] In the above explanation, one case is explained where a controlprogram for selecting from two oscillating circuits which have differentoscillation stability time and operating voltage is stored on memory ofthe watch-type information processing apparatus.

[0238] However, a program for making an information processing apparatusfunction in a same way as a watch-type information processing apparatusdisclosed in the above embodiments may be stored on a network-connectedcomputer to distribute through a telecommunication line.

[0239] Also, such program may be recorded on a recording medium (such assemiconductor memory, magnetic optical disc, or magnetic disc) readableby a computer to be distributed.

[0240] In this case, as an interface for installing the control programin the information processing apparatus, a conventional connector,optical communication using for example infrared light, or magneticcommunication using magnetic connection, may be used.

[0241] Then the program is stored on memory of the informationprocessing apparatus, and the microprocessor executes the program.

[0242] [3.6] Sixth Modification

[0243] In the above explanation, CR oscillating circuit and PLLoscillating circuit are used selectively based on the operating voltageor the oscillation stability time which is a time required for theoscillation to be stable. Namely, the CR oscillating circuit whoseoscillation becomes stable quickly is first used, then the PLLoscillating circuit which consumes small power consumption and canoscillate at a high frequency is used. Also, when the power supplyvoltage becomes lower than voltage the PLL oscillating circuit canoperate at, the CR oscillating circuit which can operate at low voltageis used.

[0244] However, the number of oscillating circuits is not limited totwo. The present invention can be applied to a case where more than twooscillating circuits are used. In this case, the selection of theoscillating circuit to be used may be made by considering, for example,the operating voltage, the oscillation stable time, and the powerconsumption of these oscillating circuits.

What is claimed is:
 1. An information processing apparatus comprising: afirst oscillating circuit for generating a first clock signal, the firstoscillating circuit being capable of operating on a power supply voltageequal to or higher than a first lowest operating voltage; a secondoscillating circuit for generating a second clock signal, the secondoscillating circuit being capable of operating on the power supplyvoltage equal to or higher than a second lowest operating voltage thatis higher than the first lowest operating voltage; a switching circuitthat, based on the power supply voltage, selects either the first clocksignal or the second clock signal to output as a clock signal; and aninformation processing unit, in synchronism with the clock signal, forperforming information processing.
 2. An information processingapparatus according to claim 1, wherein the switching circuit outputsthe first clock signal as the clock signal when the power supply voltageis equal to or higher than the first lowest operating voltage and lowerthan the second lowest operating voltage and outputs the second clocksignal as the clock signal when the power supply voltage is equal to orhigher than the second lowest operating voltage.
 3. An informationprocessing apparatus according to claim 1 or 2, further comprising apower supply voltage measuring circuit for measuring voltage of thepower supply.
 4. An information processing apparatus comprising: a firstoscillating circuit that generates a first clock signal by oscillationand has a first oscillation stability time, the first oscillationstability time being a time required for frequency of the first clocksignal becoming stable from beginning of the oscillation; a secondoscillating circuit that generates a second clock signal by oscillationand has a second oscillation stability time, the second oscillationstability time being a time required for frequency of the second clocksignal becoming stable from beginning of the oscillation, and beinglonger than the first oscillation stability time; a switching circuitfor, based on an elapsed time of the first oscillating circuit from thebeginning of the oscillation and an elapsed time of the secondoscillating circuit from the beginning of the oscillation, selecting andoutputting either the first clock signal or the second clock signal asthe clock signal; and an information processing unit for, in synchronismwith the clock signal, performing information processing.
 5. Aninformation processing apparatus according to claim 4, wherein theswitching circuit selects the first clock signal after the firstoscillation stability time has passed until the second oscillationstability time comes, and selects the second clock signal after thesecond oscillation stability time has passed.
 6. An informationprocessing apparatus according to claim 1, 2, 4, or 5, wherein the firstoscillating circuit is a CR oscillating circuit, a quartz oscillatingcircuit, or a ceramic oscillating circuit, and the second oscillatingcircuit is a PLL oscillating circuit.
 7. An information processingapparatus according to claim 3, wherein the first oscillating circuit isa CR oscillating circuit, a quartz oscillating circuit, or a ceramicoscillating circuit, and the second oscillating circuit is a PLLoscillating circuit.
 8. An information processing apparatus according toclaim 4, wherein the first oscillating circuit is a CR oscillatingcircuit, a quartz oscillating circuit, or a ceramic oscillating circuit,the second oscillating circuit is a PLL oscillating circuit, and theswitching circuit outputs the first clock signal as the clock signaluntil the PLL oscillating circuit establishes synchronization, andoutputs the second clock signal as the clock signal after the PLLoscillating circuit establishes synchronization and a state of the PLLoscillating circuit reaches a synchronization maintained state.
 9. Aninformation processing apparatus according to claim 8, wherein theswitching circuit, when the PLL oscillating circuit outputs a lockupsignal, detects completion of the synchronization.
 10. An informationprocessing apparatus according to claim 7, wherein the PLL oscillatingcircuit comprises: a voltage controlled oscillator for outputting anoscillation signal having a frequency which corresponds to a voltagecontrol signal; a phase comparator that compares phase of a referenceclock signal and phase of a comparison oscillation signal and outputs acomparison signal; a low pass filter for passing a lower component ofthe comparison signal; a divider for dividing the oscillation signal andoutputting the comparison oscillation signal; an offset voltagegenerating unit for generating an offset voltage; and an adder foradding an output signal of the low pass filter and the offset voltage tooutput the voltage control signal.
 11. An information processingapparatus according to claim 10, wherein the offset voltage generatingunit comprises: an offset voltage data storage unit for storing anoffset voltage data in advance; and a D/A converter for converting theoffset voltage data to the offset voltage.
 12. An information processingapparatus according to claim 11, wherein the PLL oscillating circuitfurther comprises an offset voltage data generating unit for, based onthe voltage control signal at a prescribed lockup state of the PLLoscillating circuit, generating the offset voltage data.
 13. Aninformation processing apparatus according to claim 10, wherein theoffset voltage generating unit comprises: a voltage dividing unit fordividing prescribed power supply voltage to generate a plurality ofdivided voltage; and a voltage selection unit for selecting one dividedvoltage from the plurality of the divided voltage as the offset voltage.14. An information processing apparatus according to claim 10, whereinthe offset voltage generating unit comprises a voltage dividing unit fordividing prescribed voltage to generate the offset voltage.
 15. Aninformation processing apparatus according to claim 12, wherein theprescribed lockup state is a state where the PLL oscillating circuit is,when the offset voltage generating unit does not output the offsetvoltage, locked up so that the oscillation signal has a prescribedfrequency.
 16. An information processing apparatus according to claim12, wherein the PLL oscillating circuit comprises: a controlled voltagedetermining unit for determining voltage of the voltage control signalat a prescribed timing; an offset data correction unit for, based on aresult of determination of the controlled voltage determining unit,correcting the offset voltage to make a new offset voltage.
 17. In acontrol method for an information processing apparatus, the informationprocessing apparatus comprising: an information processing unit for,based on a clock signal, carrying out various information processingoperations; a first oscillating circuit that generates a first clocksignal and is able to operate on power supply voltage equal to or higherthan a first lowest operating voltage, a second oscillating circuit thatgenerates a second clock signal and is able to operate on the powersupply voltage equal to or higher than a second lowest operating voltagethat is higher than the first lowest operating voltage; a switchingcircuit for, based on the power supply voltage, outputting either thefirst clock signal or the second clock signal as the clock signal; thecontrol method comprising: determining power supply voltage; outputtingby the switching circuit the first clock signal as the clock signal whenthe power supply voltage is equal to or higher than the first lowestoperating voltage and lower than the second lowest operating voltage;and outputting by the switching circuit the second clock signal as theclock signal when the power supply voltage is equal to or higher thanthe second lowest operating voltage.
 18. In a control method for aninformation processing apparatus, the information processing apparatuscomprising: a first oscillating circuit that generates a first clocksignal by oscillation and has a first oscillation stability time, thefirst oscillation stability time being a time required for frequency ofthe first clock signal becoming stable from beginning of theoscillation; a second oscillating circuit that generates a second clocksignal by oscillation and has a second oscillation stability time, thesecond oscillation stability time being a time required for frequency ofthe second clock signal becoming stable from beginning of theoscillation, and being longer than the first oscillation stability time;a switching circuit for, based on an elapsed time from the beginning ofthe oscillation of the first oscillating circuit and on an elapsed timefrom the beginning of the oscillation of the second oscillating circuit,selecting to output either the first clock signal or the second clocksignal as a clock signal; an information processing unit for, insynchronous with the clock signal, carrying out information processingoperations; the control method comprising: outputting the first clocksignal as the clock signal after the first oscillation stability timehas passed until the second oscillation stability time comes, and thesecond clock signal as the clock signal after the second oscillationstability time has passed.
 19. A method for an information processingapparatus according to claims 17 or 18 wherein the second oscillatingcircuit is a PLL oscillating circuit with a voltage controlledoscillator that outputs an oscillation signal having frequencycorresponding to voltage of a voltage control signal; and the methodfurther comprising: applying a prescribed offset voltage to the voltagecontrolled oscillator as the voltage control signal.
 20. A method for aninformation processing apparatus according to claims 19, wherein theprescribed offset voltage is a voltage of the voltage control signal,when the PLL oscillating circuit is locked up so that the oscillationsignal has a prescribed frequency.
 21. A method for an informationprocessing apparatus according to claims 19 or 20, further comprising:determining voltage of the voltage control signal at a prescribedtiming; and correcting the offset voltage to make a new offset voltagebased on determined voltage of the voltage control signal.
 22. A controlprogram executed by an information processing apparatus, the informationprocessing apparatus comprising: an information processing unit for,based on a clock signal, carrying out various information processingoperations; a first oscillating circuit that generates a first clocksignal and is able to operate on power supply voltage equal to or higherthan a first lowest operating voltage, a second oscillating circuit thatgenerates a second clock signal and is able to operate on the powersupply voltage equal to or higher than a second lowest operating voltagethat is higher than the first lowest operating voltage; and a switchingcircuit for, based on the power supply voltage, outputting either thefirst clock signal or the second clock signal as the clock signal; thecontrol program comprising the routines of: determining the power supplyvoltage; outputting to the switching circuit the first clock signal asthe clock signal when the power supply voltage is equal to or higherthan the first lowest operating voltage and is lower than the secondlowest operating voltage; and outputting to the switching circuit thesecond clock signal as the clock signal when the power supply voltage isequal to or higher than the second lowest operating voltage.
 23. Acontrol program executed by an information processing apparatus, theinformation processing apparatus comprising: an information processingunit for, in synchronous with a clock signal, carrying out variousinformation processing operations; a first oscillating circuit thatgenerates a first clock signal by oscillation and has a firstoscillation stability time, the first oscillation stability time being atime required for frequency of the first clock signal becoming stablefrom beginning of the oscillation; a second oscillating circuit thatgenerates a second clock signal by oscillation and has a secondoscillation stability time, the second oscillation stability time beinga time required for frequency of the second clock signal becoming stablefrom beginning of the oscillation, and being longer than the firstoscillation stability time; a switching circuit for, based on an elapsedtime from the beginning of the oscillation of the first oscillatingcircuit and on an elapsed time from the beginning of the oscillation ofthe second oscillating circuit, selecting to output either the firstclock signal or the second clock signal as a clock signal; the controlprogram comprising the routines of: outputting the first clock signal asthe clock signal after the first oscillation stability time has passeduntil the second oscillation stability time comes, and the second clocksignal as the clock signal after the second oscillation stability timehas passed.
 24. A control program executed by an information processingapparatus according to claims 22 or 23, wherein the second oscillatingcircuit is a PLL oscillating circuit with a voltage controlledoscillator that outputs a oscillation signal having frequencycorresponding to voltage of a voltage control signal; and the controlprogram further comprises the routines of applying a prescribed offsetvoltage to voltage of the voltage control signal.
 25. A control programexecuted by an information processing apparatus according to claim 24,wherein the prescribed offset voltage is set to voltage of the voltagecontrol signal, the voltage being a voltage attained, when the offsetvoltage is not applied to the PLL oscillating circuit, when the PLLoscillating circuit is locked up so that the oscillation signal has aprescribed frequency.
 26. A control program executed by an informationprocessing apparatus according to claim 24, further comprising theroutines of; determining voltage of the voltage control signal at aprescribed timing; and correcting the offset voltage to make a newoffset voltage based on the determined voltage of the voltage controlsignal.